Complex microelectronic devices such as modern semiconductor chips require numerous connections to other electronic components. For example, a complex microprocessor chip may require hundreds of connections to external devices.
Semiconductor chips typically have been connected to electrical conductors on mounting substrates such as circuit panels by methods such as wire bonding, tape automated bonding, and flip-chip bonding. In wire bonding, the chip is positioned on the substrate with the bottom or back surface of the chip abutting the substrate and with the contact-bearing front or top surface of the chip facing upwardly, away from the substrate. Individual fine wires are connected between the contacts on the chip and the contact pads of the substrate. In tape automated bonding, a flexible dielectric tape bearing a prefabricated array of leads is positioned over the chip and substrate, and the leads are bonded to the contacts of the chip and to pads of the substrate. In both wire bonding and conventional tape automated bonding, the pads on the substrate must be arranged outside of the area covered by the chip, so that the wires or leads spread out from the chip to the surrounding pads on the substrate.
In flip-chip bonding, the contact bearing or front surface of the chip faces towards the substrate. Each contact on the chip is joined by a solder bond to the corresponding pad on the substrate. The flip-chip technique yields a compact assembly, which occupies an area of the substrate no larger than the area of the chip itself. Such compactness reduces the overall size of the circuit. Because the speed with which an electronic digital circuit can operate is inversely related to the lengths of the conductors connecting the various elements of the circuit, saving space also helps the circuit operate faster. However, flip-chip assemblies suffer from significant problems with thermal stress. The bonds between the chip contacts and the substrate are substantially rigid. Changes in the size of the chip and of the substrate due to thermal expansion and contraction in service create substantial stresses in the bonds, which in turn can lead to fatigue failure of the bonds. Moreover, it is difficult to test the chip before attaching it to the substrate.
As described in commonly assigned U.S. Pat. Nos. 5,148,265 and 5,148,266, a chip package may include a flexible sheetlike structure referred to as a "interposer" or "chip carrier" having terminals disposed on a flexible sheetlike structure. The interposer may be disposed on the front or contact bearing surface of the chip so that the terminals face away from the chip. The terminals are connected to contacts on the chip by flexible leads. Preferably, a compliant layer is disposed between the terminals and the chip. In certain preferred embodiments, the packaged chip occupies the same area, or only a slightly larger area than the chip itself. The packaged chip can be readily tested and can be mounted to a substrate by bonding the terminals of the chip carrier to the contact pads of the substrate. In use, the terminals on the chip carrier are free to move relative to the chip. This allows the assembly to compensate for differential thermal expansion and warpage of the chip or substrate without imposing significant stresses on the bonds.
As taught in certain preferred embodiments of U.S. Pat. No. 5,518,964, commonly assigned, microelectronic assemblies incorporating flexible leads can be fabricated using a first element or connection component including a dielectric structure having leads on a bottom surface. Each such lead has a fixed end permanently attached to the dielectric structure and, typically, connected to one or more terminals on the top surface of the dielectric structure. Each such lead also has a free or tip end remote from the fixed or terminal end. Preferably, the free or tip ends of the leads are releasably attached to the dielectric structure. This element can be juxtaposed with a second microelectronic element such as a semiconductor chip or wafer, and the free ends of the leads may be bonded to contacts on such second microelectronic element. After bonding, the elements are moved vertically away from one another through a predetermined displacement, thereby detaching the free or tip ends of the leads from the bottom surface of the dielectric component and deforming the leads to a vertically extensive configuration. Preferably, a curable encapsulant is introduced between the elements and around the leads during or after the moving step, so as to provide a compliant layer between the dielectric layer and the second microelectronic element. This arrangement allows fabrication of compliant chip assemblies having advantages similar to those discussed above with respect to the '265 and '266 patents using a process which permits simultaneous connection and forming of numerous leads. In certain preferred embodiments according to the '964 patent, one of the microelectronic assemblies may include numerous semiconductor chips. For example, one of the microelectronic elements may be a wafer incorporating numerous chips, and leads on all of the chips may be connected and formed in the same operations. After these operations, the resulting large assembly can be severed to form individual units each including one or more of the chips originally present in the wafer, together with a portion of the dielectric element and the terminals thereon.
In those embodiments of the '964 invention which use a preformed connection component with leads thereon, and which register the connection component with a wafer or other microelectronic device, the spacing between the leads on the component desirably is controlled precisely. This allows registration of the free ends of the leads with contacts on a wafer or other microelectronic device. For example, certain preferred embodiments disclosed in the '964 patent use a temporary reinforcing layer overlying the dielectric layer, and also use a rigid, ring-like frame to maintain the dielectric layer and the reinforcing layer to maintain the dielectric layer in tension. These features help to control thermal expansion and contraction of the connection component during the processes used to bond the free ends of the leads to the wafer or other microelectronic component, and help to maintain the desired spacing between the lead free ends.
The aforementioned U.S. patent application Ser. No. 08/366,236 (the "'236 application") discloses still other improvements in microelectronic device fabrication. Thus, certain embodiments of the '236 application form terminals on a microelectronic connection component by etching a solid sheet of copper or another electrically conductive metal. As set forth in greater detail in the '236 application, spots of an etch resistant material such as a photoresist or a metal may be deposited on an exposed surface of the sheet, and the sheet may be exposed to an etchant by dipping or by spraying so that the etchant erodes the sheet in areas other than those covered by the spots. The resulting terminals can be in the form of posts having a unique "cooling tower" shape having a wide base, a narrow neck portion and broader tip. These terminals are particularly well suited for engagement in small hollow sockets.
Despite these and other advances in the art of making microelectronic assemblies, still further improvements would be desirable.